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8088 8-BIT HMOS MICROPROCESSOR 8088 8088-2
Y Y Y
8-Bit Data Bus Interface 16-Bit Internal Architecture Direct Addressing Capability to 1 Mbyte of Memory Direct Software Compatibility with 8086 CPU 14-Word by 16-Bit Register Set with Symmetrical Operations 24 Operand Addressing Modes
Y Y
Byte Word and Block Operations 8-Bit and 16-Bit Signed and Unsigned Arithmetic in Binary or Decimal Including Multiply and Divide Two Clock Rates 5 MHz for 8088 8 MHz for 8088-2 Available in EXPRESS Standard Temperature Range Extended Temperature Range
Y
Y
Y
Y
Y
The Intel 8088 is a high performance microprocessor implemented in N-channel depletion load silicon gate technology (HMOS-II) and packaged in a 40-pin CERDIP package The processor has attributes of both 8and 16-bit microprocessors It is directly compatible with 8086 software and 8080 8085 hardware and peripherals
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Figure 2 8088 Pin Configuration
Figure 1 8088 CPU Functional Block Diagram
August 1990
Order Number 231456-006
8088
Table 1 Pin Description
The following pin function descriptions are for 8088 systems in either minimum or maximum mode The ``local bus'' in these descriptions is the direct multiplexed bus interface connection to the 8088 (without regard to additional bus buffers) Symbol Pin No Type Name and Function AD7-AD0 9-16 I O ADDRESS DATA BUS These lines constitute the time multiplexed memory IO address (T1) and data (T2 T3 Tw T4) bus These lines are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus ``hold acknowledge'' A15-A8 2-8 39 O ADDRESS BUS These lines provide address bits 8 through 15 for the entire bus cycle (T1 - T4) These lines do not have to be latched by ALE to remain valid A15 - A8 are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus ``hold acknowledge'' A19 S6 A18 S5 35-38 O ADDRESS STATUS During T1 these are the four most significant A17 S4 A16 S3 address lines for memory operations During I O operations these lines are LOW During memory and I O operations status information is available on these lines during T2 T3 Tw and T4 S6 is always low The status of the interrupt enable flag bit (S5) is updated at the beginning of each clock cycle S4 and S3 are encoded as shown This information indicates which segment register is presently being used for data accessing These lines float to 3-state OFF during local bus ``hold acknowledge'' S4 S3 Characteristics 0 (LOW) 0 Alternate Data 0 1 Stack 1 (HIGH) 0 Code or None 1 1 Data S6 is 0 (LOW) RD 32 O READ Read strobe indicates that the processor is performing a memory or I O read cycle depending on the state of the IO M pin or S2 This signal is used to read devices which reside on the 8088 local bus RD is active LOW during T2 T3 and Tw of any read cycle and is guaranteed to remain HIGH in T2 until the 8088 local bus has floated This signal floats to 3-state OFF in ``hold acknowledge'' READY 22 I READY is the acknowledgement from the addressed memory or I O device that it will complete the data transfer The RDY signal from memory or I O is synchronized by the 8284 clock generator to form READY This signal is active HIGH The 8088 READY input is not synchronized Correct operation is not guaranteed if the set up and hold times are not met INTR 18 I INTERRUPT REQUEST is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation A subroutine is vectored to via an interrupt vector lookup table located in system memory It can be internally masked by software resetting the interrupt enable bit INTR is internally synchronized This signal is active HIGH TEST 23 I TEST input is examined by the ``wait for test'' instruction If the TEST input is LOW execution continues otherwise the processor waits in an ``idle'' state This input is synchronized internally during each clock cycle on the leading edge of CLK
2
8088
Table 1 Pin Description (Continued) Symbol NMI Pin No 17 Type I Name and Function NON-MASKABLE INTERRUPT is an edge triggered input which causes a type 2 interrupt A subroutine is vectored to via an interrupt vector lookup table located in system memory NMI is not maskable internally by software A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction This input is internally synchronized RESET causes the processor to immediately terminate its present activity The signal must be active HIGH for at least four clock cycles It restarts execution as described in the instruction set description when RESET returns LOW RESET is internally synchronized CLOCK provides the basic timing for the processor and bus controller It is asymmetric with a 33% duty cycle to provide optimized internal timing VCC is the a 5V g10% power supply pin GND are the ground pins MINIMUM MAXIMUM indicates what mode the processor is to operate in The two modes are discussed in the following sections
RESET
21
I
CLK VCC GND MN MX
19 40 1 20 33
I
I
The following pin function descriptions are for the 8088 minimum mode (i e MN MX e VCC) Only the pin functions which are unique to minimum mode are described all other pin functions are as described above Symbol Pin No Type Name and Function IO M 28 O STATUS LINE is an inverted maximum mode S2 It is used to distinguish a memory access from an I O access IO M becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle (I O e HIGH M e LOW) IO M floats to 3-state OFF in local bus ``hold acknowledge'' WR 29 O WRITE strobe indicates that the processor is performing a write memory or write I O cycle depending on the state of the IO M signal WR is active for T2 T3 and Tw of any write cycle It is active LOW and floats to 3-state OFF in local bus ``hold acknowledge'' INTA 24 O INTA is used as a read strobe for interrupt acknowledge cycles It is active LOW during T2 T3 and Tw of each interrupt acknowledge cycle ALE 25 O ADDRESS LATCH ENABLE is provided by the processor to latch the address into an address latch It is a HIGH pulse active during clock low of T1 of any bus cycle Note that ALE is never floated DT R 27 O DATA TRANSMIT RECEIVE is needed in a minimum system that desires to use a data bus transceiver It is used to control the direction of data flow through the transceiver Logically DT R is equivalent to S1 in the maximum mode and its timing is the same as for IO M (T e HIGH R e LOW) This signal floats to 3-state OFF in local ``hold acknowledge'' DEN 26 O DATA ENABLE is provided as an output enable for the data bus transceiver in a minimum system which uses the transceiver DEN is active LOW during each memory and I O access and for INTA cycles For a read or INTA cycle it is active from the middle of T2 until the middle of T4 while for a write cycle it is active from the beginning of T2 until the middle of T4 DEN floats to 3-state OFF during local bus ``hold acknowledge''
3
8088
Table 1 Pin Description (Continued) Symbol Pin No HOLD 31 30 HLDA Type Name and Function I O HOLD indicates that another master is requesting a local bus ``hold'' To be acknowledged HOLD must be active HIGH The processor receiving the ``hold'' request will issue HLDA (HIGH) as an acknowledgement in the middle of a T4 or Ti clock cycle Simultaneous with the issuance of HLDA the processor will float the local bus and control lines After HOLD is detected as being LOW the processor lowers HLDA and when the processor needs to run another cycle it will again drive the local bus and control lines HOLD and HLDA have internal pull-up resistors Hold is not an asynchronous input External synchronization should be provided if the system cannot otherwise guarantee the set up time O STATUS LINE is logically equivalent to SO in the maximum mode The combination of SSO IO M and DT R allows the system to completely decode the current bus cycle status IO M 1(HIGH) 1 1 1 0(LOW) 0 0 0 DT R 0 0 1 1 0 0 1 1 SSO 0 1 0 1 0 1 0 1 Characteristics Interrupt Acknowledge Read I O Port Write I O Port Halt Code Access Read Memory Write Memory Passive
SSO
34
The following pin function descriptions are for the 8088 8288 system in maximum mode (i e MN MX e GND) Only the pin functions which are unique to maximum mode are described all other pin functions are as described above Symbol Pin No Type Name and Function S2 S1 S0 26-28 O STATUS is active during clock high of T4 T1 and T2 and is returned to the passive state (1 1 1) during T3 or during Tw when READY is HIGH This status is used by the 8288 bus controller to generate all memory and I O access control signals Any change by S2 S1 or S0 during T4 is used to indicate the beginning of a bus cycle and the return to the passive state in T3 and Tw is used to indicate the end of a bus cycle These signals float to 3-state OFF during ``hold acknowledge'' During the first clock cycle after RESET becomes active these signals are active HIGH After this first clock they float to 3-state OFF S2 S1 S0 Characteristics 0(LOW) 0 0 Interrupt Acknowledge 0 0 1 Read I O Port 0 1 0 Write I O Port 0 1 1 Halt 1(HIGH) 0 0 Code Access 1 0 1 Read Memory 1 1 0 Write Memory 1 1 1 Passive
4
8088
Table 1 Pin Description (Continued) Symbol RQ GT0 RQ GT1 Pin No 30 31 Type IO Name and Function REQUEST GRANT pins are used by other local bus masters to force the processor to release the local bus at the end of the processor's current bus cycle Each pin is bidirectional with RQ GT0 having higher priority than RQ GT1 RQ GT has an internal pull-up resistor so may be left unconnected The request grant sequence is as follows (See Figure 8) 1 A pulse of one CLK wide from another local bus master indicates a local bus request (``hold'') to the 8088 (pulse 1) 2 During a T4 or TI clock cycle a pulse one clock wide from the 8088 to the requesting master (pulse 2) indicates that the 8088 has allowed the local bus to float and that it will enter the ``hold acknowledge'' state at the next CLK The CPU's bus interface unit is disconnected logically from the local bus during ``hold acknowledge'' The same rules as for HOLD HOLDA apply as for when the bus is released 3 A pulse one CLK wide from the requesting master indicates to the 8088 (pulse 3) that the ``hold'' request is about to end and that the 8088 can reclaim the local bus at the next CLK The CPU then enters T4 Each master-master exchange of the local bus is a sequence of three pulses There must be one idle CLK cycle after each bus exchange Pulses are active LOW If the request is made while the CPU is performing a memory cycle it will release the local bus during T4 of the cycle when all the following conditions are met 1 Request occurs on or before T2 2 Current cycle is not the low bit of a word 3 Current cycle is not the first acknowledge of an interrupt acknowledge sequence 4 A locked instruction is not currently executing If the local bus is idle when the request is made the two possible events will follow 1 Local bus will be released during the next clock 2 A memory cycle will start within 3 clocks Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied LOCK indicates that other system bus masters are not to gain control of the system bus while LOCK is active (LOW) The LOCK signal is activated by the ``LOCK'' prefix instruction and remains active until the completion of the next instruction This signal is active LOW and floats to 3-state off in ``hold acknowledge'' QUEUE STATUS provide status to allow external tracking of the internal 8088 instruction queue The queue status is valid during the CLK cycle after which the queue operation is performed QS1 0(LOW) 0 1(HIGH) 1 34 O QS0 0 1 0 1 Characteristics No Operation First Byte of Opcode from Queue Empty the Queue Subsequent Byte from Queue
LOCK
29
O
QS1 QS0
24 25
O
Pin 34 is always high in the maximum mode
5
8088
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Figure 3 Memory Organization
FUNCTIONAL DESCRIPTION Memory Organization
The processor provides a 20-bit address to memory which locates the byte being referenced The memory is organized as a linear array of up to 1 million bytes addressed as 00000(H) to FFFFF(H) The memory is logically divided into code data extra data and stack segments of up to 64K bytes each with each segment falling on 16-byte boundaries (See Figure 3) All memory references are made relative to base addresses contained in high speed segment registers The segment types were chosen based on the adMemory Reference Used Instructions Stack Local Data External (Global) Data Segment Register Used CODE (CS) STACK (SS) DATA (DS) EXTRA (ES)
dressing needs of programs The segment register to be selected is automatically chosen according to the rules of the following table All information in one segment type share the same logical attributes (e g code or data) By structuring memory into relocatable areas of similar characteristics and by automatically selecting segment registers programs are shorter faster and more structured Word (16-bit) operands can be located on even or odd address boundaries For address and data operands the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location The BIU will automatically execute two fetch or write cycles for 16-bit operands
Segment Selection Rule Automatic with all instruction prefetch All stack pushes and pops Memory references relative to BP base register except data references Data references when relative to stack destination of string operation or explicity overridden Destination of string operations Explicitly selected using a segment override
6
8088
Certain locations in memory are reserved for specific CPU operations (See Figure 4) Locations from addresses FFFF0H through FFFFFH are reserved for operations including a jump to the initial system initialization routine Following RESET the CPU will always begin execution at location FFFF0H where the jump must be located Locations 00000H through 003FFH are reserved for interrupt operations Fourbyte pointers consisting of a 16-bit segment address and a 16-bit offset address direct program flow to one of the 256 possible interrupt service routines The pointer elements are assumed to have been stored at their respective places in reserved memory prior to the occurrence of interrupts figuration The definition of a certain subset of the pins changes dependent on the condition of the strap pin When the MN MX pin is strapped to GND the 8088 defines pins 24 through 31 and 34 in maximum mode When the MN MX pin is strapped to VCC the 8088 generates bus control signals itself on pins 24 through 31 and 34 The minimum mode 8088 can be used with either a multiplexed or demultiplexed bus The multiplexed bus configuration is compatible with the MCS-85 multiplexed bus peripherals This configuration (See Figure 5) provides the user with a minimum chip count system This architecture provides the 8088 processing power in a highly integrated form The demultiplexed mode requires one latch (for 64K addressability) or two latches (for a full megabyte of addressing) A third latch can be used for buffering if the address bus loading requires it A transceiver can also be used if data bus buffering is required (See Figure 6) The 8088 provides DEN and DT R to control the transceiver and ALE to latch the addresses This configuration of the minimum mode provides the standard demultiplexed bus structure with heavy bus buffering and relaxed bus timing requirements The maximum mode employs the 8288 bus controller (See Figure 7) The 8288 decodes status lines S0 S1 and S2 and provides the system with all bus control signals Moving the bus control to the 8288 provides better source and sink current capability to the control lines and frees the 8088 pins for extended large system features Hardware lock queue status and two request grant interfaces are provided by the 8088 in maximum mode These features allow co-processors in local bus and remote bus configurations
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Minimum and Maximum Modes
The requirements for supporting minimum and maximum 8088 systems are sufficiently different that they cannot be done efficiently with 40 uniquely defined pins Consequently the 8088 is equipped with a strap pin (MN MX) which defines the system con-
Figure 4 Reserved Memory Locations
7
8088
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Figure 5 Multiplexed Bus Configuration
8
8088
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Figure 6 Demultiplexed Bus Configuration
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Figure 7 Fully Buffered System Using Bus Controller
9
8088
id throughout each bus cycle In addition the bus can be demultiplexed at the processor with a single address latch if a standard non-multiplexed bus is desired for the system Each processor bus cycle consists of at least four CLK cycles These are referred to as T1 T2 T3 and T4 (See Figure 8) The address is emitted from the processor during T1 and data transfer occurs on the bus during T3 and T4 T2 is used primarily for chang-
Bus Operation
The 8088 address data bus is broken into three parts the lower eight address data bits (AD0 - AD7) the middle eight address bits (A8-A15) and the upper four address bits (A16-A19) The address data bits and the highest four address bits are time multiplexed This technique provides the most efficient use of pins on the processor permitting the use of a standard 40 lead package The middle eight address bits are not multiplexed i e they remain val-
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Figure 8 Basic System Timing
10
8088
ing the direction of the bus during read operations In the event that a ``NOT READY'' indication is given by the addressed device ``wait'' states (Tw) are inserted between T3 and T4 Each inserted ``wait'' state is of the same duration as a CLK cycle Periods can occur between 8088 driven bus cycles These are referred to as ``idle'' states (Ti) or inactive CLK cycles The processor uses these cycles for internal housekeeping During T1 of any bus cycle the ALE (address latch enable) signal is emitted (by either the processor or the 8288 bus controller depending on the MN MX strap) At the trailing edge of this pulse a valid address and certain status information for the cycle may be latched Status bits S0 S1 and S2 are used by the bus controller in maximum mode to identify the type of bus transaction according to the following table S2 0(LOW) 0 0 0 1(HIGH) 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Characteristics Interrupt Acknowledge Read I O Write I O Halt Instruction Fetch Read Data from Memory Write Data to Memory Passive (No Bus Cycle) which use register DX as a pointer have full address capability while the direct I O instructions directly address one or two of the 256 I O byte locations in page 0 of the I O address space I O ports are addressed in the same manner as memory locations Designers familiar with the 8085 or upgrading an 8085 design should note that the 8085 addresses I O with an 8-bit address on both halves of the 16bit address bus The 8088 uses a full 16-bit address on its lower 16 address lines
EXTERNAL INTERFACE Processor Reset and Initialization
Processor initialization or start up is accomplished with activation (HIGH) of the RESET pin The 8088 RESET is required to be HIGH for greater than four clock cycles The 8088 will terminate operations on the high-going edge of RESET and will remain dormant as long as RESET is HIGH The low-going transition of RESET triggers an internal reset sequence for approximately 7 clock cycles After this interval the 8088 operates normally beginning with the instruction in absolute locations FFFF0H (See Figure 4) The RESET input is internally synchronized to the processor clock At initialization the HIGH to LOW transition of RESET must occur no sooner than 50 ms after power up to allow complete initialization of the 8088 NMI asserted prior to the 2nd clock after the end of RESET will not be honored If NMI is asserted after that point and during the internal reset sequence the processor may execute one instruction before responding to the interrupt A hold request active immediately after RESET will be honored before the first instruction fetch All 3-state outputs float to 3-state OFF during RESET Status is active in the idle state for the first clock after RESET becomes active and then floats to 3-state OFF ALE and HLDA are driven low
Status bits S3 through S6 are multiplexed with high order address bits and are therefore valid during T2 through T4 S3 and S4 indicate which segment register was used for this bus cycle in forming the address according to the following table S4 0(LOW) 0 1(HIGH) 1 S3 0 1 0 1 Characteristics Alternate Data (Extra Segment) Stack Code or None Data
S5 is a reflection of the PSW interrupt enable bit S6 is always equal to 0
Interrupt Operations
Interrupt operations fall into two classes software or hardware initiated The software initiated interrupts and software aspects of hardware interrupts are specified in the instruction set description in the iAPX 88 book or the iAPX 86 88 User's Manual Hardware interrupts can be classified as nonmaskable or maskable
I O Addressing
In the 8088 I O operations can address up to a maximum of 64K I O registers The I O address appears in the same format as the memory address on bus lines A15-A0 The address lines A19-A16 are zero in I O operations The variable I O instructions
11
8088
Interrupts result in a transfer of control to a new program location A 256 element table containing address pointers to the interrupt service program locations resides in absolute locations 0 through 3FFH (See Figure 4) which are reserved for this purpose Each element in the table is 4 bytes in size and corresponds to an interrupt ``type '' An interrupting device supplies an 8-bit type number during the interrupt acknowledge sequence which is used to vector through the appropriate element to the new interrupt service program location enable bit will be zero unless specifically set by an instruction During the response sequence (See Figure 9) the processor executes two successive (back to back) interrupt acknowledge cycles The 8088 emits the LOCK signal (maximum mode only) from T2 of the first bus cycle until T2 of the second A local bus ``hold'' request will not be honored until the end of the second bus cycle In the second bus cycle a byte is fetched from the external interrupt system (e g 8259A PIC) which identifies the source (type) of the interrupt This byte is multiplied by four and used as a pointer into the interrupt vector lookup table An INTR signal left HIGH will be continually responded to within the limitations of the enable bit and sample period The interrupt return instruction includes a flags pop which returns the status of the original interrupt enable bit when it restores the flags
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrupt (NMI) pin which has higher priority than the maskable interrupt request (INTR) pin A typical use would be to activate a power failure routine The NMI is edge-triggered on a LOW to HIGH transition The activation of this pin causes a type 2 interrupt NMI is required to have a duration in the HIGH state of greater than two clock cycles but is not required to be synchronized to the clock Any higher going transition of NMI is latched on-chip and will be serviced at the end of the current instruction or between whole moves (2 bytes in the case of word moves) of a block type instruction Worst case response to NMI would be for multiply divide and variable shift instructions There is no specification on the occurrence of the low-going edge it may occur before during or after the servicing of NMI Another highgoing edge triggers another response if it occurs after the start of the NMI procedure The signal must be free of logical spikes in general and be free of bounces on the low-going edge to avoid triggering extraneous responses
HALT
When a software HALT instruction is executed the processor indicates that it is entering the HALT state in one of two ways depending upon which mode is strapped In minimum mode the processor issues ALE delayed by one clock cycle to allow the system to latch the halt status Halt status is available on IO M DT R and SSO In maximum mode the processor issues appropriate HALT status on S2 S1 and S0 and the 8288 bus controller issues one ALE The 8088 will not leave the HALT state when a local bus hold is entered while in HALT In this case the processor reissues the HALT indicator at the end of the local bus hold An interrupt request or RESET will force the 8088 out of the HALT state
Maskable Interrupt (INTR)
The 8088 provides a single interrupt request input (INTR) which can be masked internally by software with the resetting of the interrupt enable (IF) flag bit The interrupt request signal is level triggered It is internally synchronized during each clock cycle on the high-going edge of CLK To be responded to INTR must be present (HIGH) during the clock period preceding the end of the current instruction or the end of a whole move for a block type instruction During interrupt response sequence further interrupts are disabled The enable bit is reset as part of the response to any interrupt (INTR NMI software interrupt or single step) although the FLAGS register which is automatically pushed onto the stack reflects the state of the processor prior to the interrupt Until the old FLAGS register is restored the
Read Modify Write (Semaphore) Operations via LOCK
The LOCK status information is provided by the processor when consecutive bus cycles are required during the execution of an instruction This allows the processor to perform read modify write operations on memory (via the ``exchange register with memory'' instruction) without another system bus master receiving intervening memory cycles This is useful in multiprocessor system configurations to accomplish ``test and set lock'' operations The LOCK signal is activated (LOW) in the clock cycle following decoding of the LOCK prefix instruction It is deactivated at the end of the last bus cycle of the instruction following the LOCK prefix While LOCK is active a request on a RQ GT pin will be recorded and then honored at the end of the LOCK
12
8088
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Figure 9 Interrupt Acknowledge Sequence
External Synchronization via TEST
As an alternative to interrupts the 8088 provides a single software-testable input pin (TEST) This input is utilized by executing a WAIT instruction The single WAIT instruction is repeatedly executed until the TEST input goes active (LOW) The execution of WAIT does not consume bus cycles once the queue is full If a local bus request occurs during WAIT execution the 8088 3-states all output drivers If interrupts are enabled the 8088 will recognize interrupts and process them The WAIT instruction is then refetched and reexecuted
Basic System Timing
In minimum mode the MN MX pin is strapped to VCC and the processor emits bus control signals compatible with the 8085 bus structure In maximum mode the MN MX pin is strapped to GND and the processor emits coded status information which the 8288 bus controller uses to generate MULTIBUS compatible bus control signals
going) edge of this signal is used to latch the address information which is valid on the address data bus (AD0 - AD7) at this time into the 8282 8283 latch Address lines A8 through A15 do not need to be latched because they remain valid throughout the bus cycle From T1 to T4 the IO M signal indicates a memory or I O operation At T2 the address is removed from the address data bus and the bus goes to a high impedance state The read control signal is also asserted at T2 The read (RD) signal causes the addressed device to enable its data bus drivers to the local bus Some time later valid data will be available on the bus and the addressed device will drive the READY line HIGH When the processor returns the read signal to a HIGH level the addressed device will again 3-state its bus drivers If a transceiver is required to buffer the 8088 local bus signals DT R and DEN are provided by the 8088 A write cycle also begins with the assertion of ALE and the emission of the address The IO M signal is again asserted to indicate a memory or I O write operation In T2 immediately following the address emission the processor emits the data to be written into the addressed location This data remains valid until at least the middle of T4 During T2 T3 and Tw the processor asserts the write control signal The write (WR) signal becomes active at the beginning of T2 as opposed to the read which is delayed somewhat into T2 to provide time for the bus to float
System Timing
(See Figure 8)
Minimum System
The read cycle begins in T1 with the assertion of the address latch enable (ALE) signal The trailing (low
13
8088
The basic difference between the interrupt acknowledge cycle and a read cycle is that the interrupt acknowledge (INTA) signal is asserted in place of the read (RD) signal and the address bus is floated (See Figure 9) In the second of two successive INTA cycles a byte of information is read from the data bus as supplied by the interrupt system logic (i e 8259A priority interrupt controller) This byte identifies the source (type) of the interrupt It is multiplied by four and used as a pointer into the interrupt vector lookup table as described earlier the same way the 8086 does with the distinction of handling only 8 bits at a time Sixteen-bit operands are fetched or written in two consecutive bus cycles Both processors will appear identical to the software engineer with the exception of execution time The internal register structure is identical and all instructions have the same end result The differences between the 8088 and 8086 are outlined below The engineer who is unfamiliar with the 8086 is referred to the iAPX 86 88 User's Manual Chapters 2 and 4 for function description and instruction set information Internally there are three differences between the 8088 and the 8086 All changes are related to the 8-bit bus interface The queue length is 4 bytes in the 8088 whereas the 8086 queue contains 6 bytes or three words The queue was shortened to prevent overuse of the bus by the BIU when prefetching instructions This was required because of the additional time necessary to fetch instructions 8 bits at a time
Bus Timing Systems
(See Figure 10)
Medium Complexity
For medium complexity systems the MN MX pin is connected to GND and the 8288 bus controller is added to the system as well as a latch for latching the system address and a transceiver to allow for bus loading greater than the 8088 is capable of handling Signals ALE DEN and DT R are generated by the 8288 instead of the processor in this configuration although their timing remains relatively the same The 8088 status outputs (S2 S1 and S0) provide type of cycle information and become 8288 inputs This bus cycle information specifies read (code data or I O) write (data or I O) interrupt acknowledge or software halt The 8288 thus issues control signals specifying memory read or write I O read or write or interrupt acknowledge The 8288 provides two types of write strobes normal and advanced to be applied as required The normal write strobes have data valid at the leading edge of write The advanced write strobes have the same timing as read strobes and hence data is not valid at the leading edge of write The transceiver receives the usual T and OE inputs from the 8288's DT R and DEN outputs The pointer into the interrupt vector table which is passed during the second INTA cycle can derive from an 8259A located on either the local bus or the system bus If the master 8289A priority interrupt controller is positioned on the local bus a TTL gate is required to disable the transceiver when reading from the master 8259A during the interrupt acknowledge sequence and software ``poll''
To further optimize the queue the prefetching algorithm was changed The 8088 BIU will fetch a new instruction to load into the queue each time there is a 1 byte hole (space available) in the queue The 8086 waits until a 2-byte space is available
The internal execution time of the instruction set
is affected by the 8-bit interface All 16-bit fetches and writes from to memory take an additional four clock cycles The CPU is also limited by the speed of instruction fetches This latter problem only occurs when a series of simple operations occur When the more sophisticated instructions of the 8088 are being used the queue has time to fill and the execution proceeds as fast as the execution unit will allow The 8088 and 8086 are completely software compatible by virtue of their identical execution units Software that is system dependent may not be completely transferable but software that is not system dependent will operate equally as well on an 8088 and an 8086 The hardware interface of the 8088 contains the major differences between the two CPUs The pin assignments are nearly identical however with the following functional changes
A8 - A15 These pins are only address outputs
on the 8088 These address lines are latched internally and remain valid throughout a bus cycle in a manner similar to the 8085 upper address lines BHE has no meaning on the 8088 and has been eliminated
The 8088 Compared to the 8086
The 8088 CPU is an 8-bit processor designed around the 8086 internal structure Most internal functions of the 8088 are identical to the equivalent 8086 functions The 8088 handles the external bus
14
8088
SSO provides the SO status information in the
minimum mode This output occurs on pin 34 in minimum mode only DT R IO M and SSO provide the complete bus status in minimum mode
IO M has been inverted to be compatible with the
MCS-85 bus structure
ALE is delayed by one clock cycle in the minimum mode when entering HALT to allow the status to be latched with ALE
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Figure 10 Medium Complexity System Timing
15
8088
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias Case Temperature (Plastic) Case Temperature (CERDIP) Storage Temperature Voltage on Any Pin with Respect to Ground Power Dissipation 0 C to a 70 C 0 C to a 95 C 0 C to a 75 C
b 65 C to a 150 C b 1 0 to a 7V
NOTICE This is a production data sheet The specifications are subject to change without notice
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
2 5 Watt
D C CHARACTERISTICS
(TA e 0 C to 70 C TCASE (Plastic) e 0 C to 95 C TCASE (CERDIP) e 0 C to 75 C TA e 0 C to 55 C and TCASE e 0 C to 75 C for P8088-2 only TA is guaranteed as long as TCASE is not exceeded) (VCC e 5V g10% for 8088 VCC e 5V g5% for 8088-2 and Extended Temperature EXPRESS) Symbol VIL VIH VOL VOH ICC Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 8088 Power Supply Current 8088-2 P8088 Input Leakage Current Output and I O Leakage Current Clock Input Low Voltage Clock Input High Voltage Capacitance If Input Buffer (All Input Except AD0 -AD7 RQ GT) Capacitance of I O Buffer AD0 -AD7 RQ GT)
b0 5
Min
b0 5
Max
a0 8
Units V V V V
Test Conditions (Note 1) (Notes 1 2) IOL e 2 0 mA IOH e b 400 mA TA e 25 C
20
VCC a 0 5 0 45
24 340 350 250
g10 g10
mA
ILI ILO VCL VCH CIN
mA mA V V pF
0V s VIN s VCC (Note 3) 0 45V s VOUT s VCC
a0 6
39
VCC a 1 0 15
fc e 1 MHz
CIO
15
pF
fc e 1 MHz
NOTES 1 VIL tested with MN MX Pin e 0V VIH tested with MN MX Pin e 5V MN MX Pin is a strap Pin 2 Not applicable to RQ GT0 and RQ GT1 Pins (Pins 30 and 31) 3 HOLD and HLDA ILI Min e 30 mA Max e 500 mA
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8088
A C CHARACTERISTICS
(TA e 0 C to 70 C TCASE (Plastic) e 0 C to 95 C TCASE (CERDIP) e 0 C to 75 C TA e 0 C to 55 C and TCASE e 0 C to 80 C for P8088-2 only TA is guaranteed as long as TCASE is not exceeded) (VCC e 5V g10% for 8088 VCC e 5V g5% for 8088-2 and Extended Temperature EXPRESS) MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS Symbol TCLCL TCLCH TCHCL TCH1CH2 TCL2CL2 TDVCL TCLDX TR1VCL TCLR1X TRYHCH TCHRYX TRYLCL THVCH TINVCH TILIH TIHIL Parameter CLK Cycle Period CLK Low Time CLK High Time CLK Rise Time CLK Fall Time Data in Setup Time Data in Hold Time RDY Setup Time into 8284 (Notes 1 2) RDY Hold Time into 8284 (Notes 1 2) READY Setup Time into 8088 READY Hold Time into 8088 READY Inactive to CLK (Note 3) HOLD Setup Time INTR NMI TEST Setup Time (Note 2) Input Rise Time (Except CLK) Input Fall Time (Except CLK) 30 10 35 0 118 30
b8
8088 Min 200 118 69 10 10 Max 500
8088-2 Min 125 68 44 10 10 20 10 35 0 68 20
b8
Max 500
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Test Conditions
From 1 0V to 3 5V From 3 5V to 1 0V
35 30 20 12
20 15 20 12
ns ns
From 0 8V to 2 0V From 2 0V to 0 8V
17
8088
A C CHARACTERISTICS (Continued)
TIMING RESPONSES Symbol TCLAV TCLAX TCLAZ TLHLL TCLLH TCHLL TLLAX TCLDV TCHDX TWHDX TCVCTV Parameter Address Valid Delay Address Hold Time Address Float Delay ALE Width ALE Active Delay ALE Inactive Delay Address Hold Time to ALE Inactive Data Valid Delay Data Hold Time Data Hold Time after WR Control Active Delay 1 TCHCL b 10 10 10 TCLCH b 30 10 10 10 0 10 10 TCLCL b 45 10 2TCLCL b 75 2TCLCL b 60 TCLCH b 60 20 12 160 165 150 110 110 110 110 8088 Min 10 10 TCLAX TCLCH b 20 80 85 TCHCL b 10 10 10 TCLCH b 30 10 10 10 0 10 10 TCLCL b 40 10 2TCLCL b 50 2TCLCL b 40 TCLCH b 40 20 12 100 100 80 70 60 70 60 80 Max 110 8088-2 Min 10 10 TCLAX TCLCH b 10 50 55 50 Max 60 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns From 0 8V to 2 0V From 2 0V to 0 8V Test Conditions
TCHCTV Control Active Delay 2 TCVCTX TAZRL TCLRL TCLRH TRHAV TCLHAV TRLRH TWLWH TAVAL TOLOH TOHOL Control Inactive Delay Address Float to READ Active RD Active Delay RD Inactive Delay RD Inactive to Next Address Active HLDA Valid Delay RD Width WR Width Address Valid to ALE Low Output Rise Time Output Fall Time
NOTES 1 Signal at 8284A shown for reference only See 8284A data sheet for the most recent specifications 2 Set up requirement for asynchronous signal only to guarantee recognition at next CLK 3 Applies only to T2 state (8 ns into T3 state)
18
8088
A C TESTING INPUT OUTPUT WAVEFORM
A C TESTING LOAD CIRCUIT
231456 - 11 A C Testing Inputs are driven at 2 4V for a logic ``1'' and 0 45V for a logic ``0'' Timing measurements are made at 1 5V for both a logic ``1'' and logic ``0''
231456 - 12 CL Includes Jig Capacitance
WAVEFORMS
BUS TIMING MINIMUM MODE SYSTEM
231456 - 13
19
8088
WAVEFORMS (Continued)
BUS TIMING MINIMUM MODE SYSTEM (Continued)
231456 - 14
NOTES 1 All signals switch between VOH and VOL unless otherwise specified 2 RDY is sampled near the end of T2 T3 Tw to determine if Tw machines states are to be inserted 3 Two INTA cycles run back-to-back The 8088 local ADDR DATA bus is floating during both INTA cycles Control signals are shown for the second INTA cycle 4 Signals at 8284 are shown for reference only 5 All timing measurements are made at 1 5V unless otherwise noted
20
8088
A C CHARACTERISTICS
MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) TIMING REQUIREMENTS Symbol TCLCL TCLCH TCHCL TCH1CH2 TCL2CL1 TDVCL TCLDX TR1VCL TCLR1X TRYHCH TCHRYX TRYLCL TINVCH TGVCH TCHGX TILIH TIHIL Parameter CLK Cycle Period CLK Low Time CLK High Time CLK Rise Time CLK Fall Time Data in Setup Time Data in Hold Time RDY Setup Time into 8284 (Notes 1 2) RDY Hold Time into 8284 (Notes 1 2) READY Setup Time into 8088 READY Hold Time into 8088 READY Inactive to CLK (Note 4) Setup Time for Recognition (INTR NMI TEST) (Note 2) RQ GT Setup Time RQ Hold Time into 8088 Input Rise Time (Except CLK) Input Fall Time (Except CLK) 30 10 35 0 118 30
b8
8088 Min 200 118 69 10 10 Max 500
8088-2 Min 125 68 44 10 10 20 10 35 0 68 20
b8
Max 500
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Test Conditions
From 1 0V to 3 5V From 3 5V to 1 0V
30 30 40 20 12
15 15 30 20 12
ns ns
From 0 8V to 2 0V From 2 0V to 0 8V
21
8088
A C CHARACTERISTICS (Continued)
TIMING RESPONSES Symbol TCLML TCLMH TRYHSH TCHSV TCLSH TCLAV TCLAX TCLAZ TSVLH TSVMCH TCLLH TCLMCH TCHLL TCLMCL TCLDV TCHDX TCVNV TCVNX TAZRL TCLRL TCLRH TRHAV TCHDTL TCHDTH TCLGL TCLGH TRLRH TOLOH TOHOL Parameter 8088 Min 10 Max 35 35 110 110 130 110 80 15 15 15 15 15 15 110 45 45 10 10 10 10 TCLAX 8088-2 Units Min Max 10 35 ns 10 35 65 60 70 60 50 15 15 15 15 15 15 60 45 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 80 ns ns ns ns ns ns ns ns ns ns Test Conditions
Command Active Delay (Note 1) Command Inactive Delay 10 (Note 1) READY Active to Status Passive (Note 3) Status Active Delay 10 Status Inactive Delay 10 Address Valid Delay 10 Address Hold Time 10 Address Float Delay TCLAX Status Valid to ALE High (Note 1) Status Valid to MCE High (Note 1) CLK Low to ALE Valid (Note 1) CLK Low to MCE (Note 1) ALE Inactive Delay (Note 1) MCE Inactive Delay (Note 1) Data Valid Delay 10 Data Hold Time 10 Control Active Delay 5 (Note 1) Control Inactive Delay 10 (Note 1) Address Float to 0 Read Active RD Active Delay 10 RD Inactive Delay 10 RD Inactive to Next TCLCL b 45 Address Active Direction Control Active Delay (Note 1) Direction Control Inactive Delay (Note 1) GT Active Delay GT Inactive Delay RD Width 2TCLCL b 75 Output Rise Time Output Fall Time
10 10 5 10 0
CL e 20 - 100 pF for All 8088 Outputs in Addition to Internal Loads
165 150
10 10 TCLCL b 40
50 30 85 85 2TCLCL b 50 20 12
50 30 50 50 20 12
From 0 8V to 2 0V From 2 0V to 0 8V
NOTES 1 Signal at 8284 or 8288 shown for reference only 2 Setup requirement for asynchronous signal only to guarantee recognition at next CLK 3 Applies only to T3 and wait states 4 Applies only to T2 state (8 ns into T3 state)
22
8088
A C TESTING INPUT OUTPUT WAVEFORM
A C TESTING LOAD CIRCUIT
231456 - 11 A C Testing Inputs are driven at 2 4V for a logic ``1'' and 0 45V for a logic ``0'' Timing measurements are made at 1 5V for both a logic ``1'' and logic ``0''
231456 - 12 CL Includes Jig Capacitance
WAVEFORMS (Continued)
BUS TIMING MAXIMUM MODE SYSTEM
231456 - 15
23
8088
WAVEFORMS (Continued)
BUS TIMING MAXIMUM MODE SYSTEM (USING 8288)
NOTES 231456 - 16 1 All signals switch between VOH and VOL unless otherwise specified 2 RDY is sampled near the end of T2 T3 Tw to determine if Tw machines states are to be inserted 3 Cascade address is valid between first and second INTA cycles 4 Two INTA cycles run back-to-back The 8088 local ADDR DATA bus is floating during both INTA cycles Control for pointer address is shown for second INTA cycle 5 Signals at 8284 or 8288 are shown for reference only 6 The issuance of the 8288 command and control signals (MRDC MWTC AMWC IORC IOWC AIOWC INTA and DEN) lags the active high 8288 CEN 7 All timing measurements are made at 1 5V unless otherwise noted 8 Status inactive in state just prior to T4
24
8088
WAVEFORMS (Continued)
ASYNCHRONOUS SIGNAL RECOGNITION BUS LOCK SIGNAL TIMING (MAXIMUM MODE ONLY)
NOTE 231456 - 17 1 Setup requirements for asynchronous signals only to guarantee recognition at next CLK
231456 - 18
REQUEST GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
NOTE 1 The coprocessor may not drive the busses outside the region shown without risking contention
231456 - 19
HOLD HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
231456 - 20
25
8088
8086 8088 Instruction Set Summary
Mnemonic and Description DATA TRANSFER MOV e Move Register Memory to from Register Immediate to Register Memory Immediate to Register Memory to Accumulator Accumulator to Memory Register Memory to Segment Register Segment Register to Register Memory PUSH e Push Register Memory Register Segment Register POP e Pop Register Memory Register Segment Register XCHG e Exchange Register Memory with Register Register with Accumulator IN e Input from Fixed Port Variable Port OUT e Output to Fixed Port Variable Port XLAT e Translate Byte to AL LEA e Load EA to Register LDS e Load Pointer to DS LES e Load Pointer to ES LAHF e Load AH with Flags SAHF e Store AH into Flags PUSHF e Push Flags POPF e Pop Flags 1110011w 1110111w 11010111 10001101 11000101 11000100 10011111 10011110 10011100 10011101 mod reg r m mod reg r m mod reg r m port 1110010w 1110110w port 1000011w 1 0 0 1 0 reg mod reg r m 10001111 0 1 0 1 1 reg 0 0 0 reg 1 1 1 mod 0 0 0 r m 11111111 0 1 0 1 0 reg 0 0 0 reg 1 1 0 mod 1 1 0 r m 76543210 100010dw 1100011w 1 0 1 1 w reg 1010000w 1010001w 10001110 10001100 76543210 mod reg rm data data if w e 1 addr-high addr-high data if w e 1 76543210 76543210 Instruction Code
mod 0 0 0 r m data addr-low addr-low mod 0 reg r m mod 0 reg r m
26
8088
8086 8088 Instruction Set Summary (Continued)
Mnemonic and Description ARITHMETIC ADD e Add Reg Memory with Register to Either Immediate to Register Memory Immediate to Accumulator ADC e Add with Carry Reg Memory with Register to Either Immediate to Register Memory Immediate to Accumulator INC e Increment Register Memory Register AAA e ASCII Adjust for Add BAA e Decimal Adjust for Add SUB e Subtract Reg Memory and Register to Either Immediate from Register Memory Immediate from Accumulator SSB e Subtract with Borrow Reg Memory and Register to Either Immediate from Register Memory Immediate from Accumulator DEC e Decrement Register memory Register NEG e Change sign CMP e Compare Register Memory and Register Immediate with Register Memory Immediate with Accumulator AAS e ASCII Adjust for Subtract DAS e Decimal Adjust for Subtract MUL e Multiply (Unsigned) IMUL e Integer Multiply (Signed) AAM e ASCII Adjust for Multiply DIV e Divide (Unsigned) IDIV e Integer Divide (Signed) AAD e ASCII Adjust for Divide CBW e Convert Byte to Word CWD e Convert Word to Double Word 001110dw 100000sw 0011110w 00111111 00101111 1111011w 1111011w 11010100 1111011w 1111011w 11010101 10011000 10011001 mod 1 0 0 r m mod 1 0 1 r m 00001010 mod 1 1 0 r m mod 1 1 1 r m 00001010 mod reg r m mod 1 1 1 r m data data data if w e 1 data if s w e 01 1111111w 0 1 0 0 1 reg 1111011w mod 0 1 1 r m mod 0 0 1 r m 000110dw 100000sw 000111w mod reg r m mod 0 1 1 r m data data data if w e 1 data if s w e 01 001010dw 100000sw 0010110w mod reg r m mod 1 0 1 r m data data data if w e 1 data if s w e 01 1111111w 0 1 0 0 0 reg 00110111 00100111 mod 0 0 0 r m 000100dw 100000sw 0001010w mod reg r m mod 0 1 0 r m data data data if w e 1 data if s w e 01 000000dw 100000sw 0000010w mod reg r m mod 0 0 0 r m data data data if w e 1 data if s w e 01 76543210 Instruction Code 76543210 76543210 76543210
27
8088
8086 8088 Instruction Set Summary (Continued)
Mnemonic and Description LOGIC NOT e Invert SHL SAL e Shift Logical Arithmetic Left SHR e Shift Logical Right SAR e Shift Arithmetic Right ROL e Rotate Left ROR e Rotate Right RCL e Rotate Through Carry Flag Left RCR e Rotate Through Carry Right AND e And Reg Memory and Register to Either Immediate to Register Memory Immediate to Accumulator TEST e And Function to Flags No Result Register Memory and Register Immediate Data and Register Memory Immediate Data and Accumulator OR e Or Reg Memory and Register to Either Immediate to Register Memory Immediate to Accumulator XOR e Exclusive or Reg Memory and Register to Either Immediate to Register Memory Immediate to Accumulator STRING MANIPULATION REP e Repeat MOVS e Move Byte Word CMPS e Compare Byte Word SCAS e Scan Byte Word LODS e Load Byte Wd to AL AX STOS e Stor Byte Wd from AL A CONTROL TRANSFER CALL e Call Direct Within Segment Indirect Within Segment Direct Intersegment 11101000 11111111 10011010 disp-low mod 0 1 0 r m offset-low seg-low Indirect Intersegment 11111111 mod 0 1 1 r m offset-high seg-high disp-high 1111001z 1010010w 1010011w 1010111w 1010110w 1010101w 001100dw 1000000w 0011010w mod reg r m mod 1 1 0 r m data data data if w e 1 data if w e 1 000010dw 1000000w 0000110w mod reg r m mod 0 0 1 r m data data data if w e 1 data if w e 1 1000010w 1111011w 1010100w mod reg r m mod 0 0 0 r m data data data if w e 1 data if w e 1 001000dw 1000000w 0010010w mod reg r m mod 1 0 0 r m data data data if w e 1 data if w e 1 76543210 1111011w 110100vw 110100vw 110100vw 110100vw 110100vw 110100vw 110100vw Instruction Code 76543210 mod 0 1 0 r m mod 1 0 0 r m mod 1 0 1 r m mod 1 1 1 r m mod 0 0 0 r m mod 0 0 1 r m mod 0 1 0 r m mod 0 1 1 r m 76543210 76543210
28
8088
8086 8088 Instruction Set Summary (Continued)
Mnemonic and Description JMP e Unconditional Jump Direct Within Segment Direct Within Segment-Short Indirect Within Segment Direct Intersegment 76543210 11101001 11101011 11111111 11101010 Instruction Code 76543210 disp-low disp mod 1 0 0 r m offset-low seg-low Indirect Intersegment RET e Return from CALL Within Segment Within Seg Adding Immed to SP Intersegment Intersegment Adding Immediate to SP JE JZ e Jump on Equal Zero JL JNGE e Jump on Less Not Greater or Equal JLE JNG e Jump on Less or Equal Not Greater JB JNAE e Jump on Below Not Above or Equal JBE JNA e Jump on Below or Equal Not Above JP JPE e Jump on Parity Parity Even JO e Jump on Overflow JS e Jump on Sign JNE JNZ e Jump on Not Equal Not Zero JNL JGE e Jump on Not Less Greater or Equal JNLE JG e Jump on Not Less or Equal Greater JNB JAE e Jump on Not Below Above or Equal JNBE JA e Jump on Not Below or Equal Above JNP JPO e Jump on Not Par Par Odd JNO e Jump on Not Overflow JNS e Jump on Not Sign LOOP e Loop CX Times LOOPZ LOOPE e Loop While Zero Equal LOOPNZ LOOPNE e Loop While Not Zero Equal JCXZ e Jump on CX Zero INT e Interrupt Type Specified Type 3 INTO e Interrupt on Overflow IRET e Interrupt Return 11001101 11001100 11001110 11001111 type 11000011 11000010 11001011 11001010 01110100 01111100 01111110 01110010 01110110 01111010 01110000 01111000 01110101 01111101 01111111 01110011 01110111 01111011 01110001 01111001 11100010 11100001 11100000 11100011 data-low disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp data-high data-low data-high 11111111 mod 1 0 1 r m offset-high seg-high 76543210 disp-high
29
8088
8086 8088 Instruction Set Summary (Continued)
Mnemonic and Description 76543210 PROCESSOR CONTROL CLC e Clear Carry CMC e Complement Carry STC e Set Carry CLD e Clear Direction STD e Set Direction CLI e Clear Interrupt STI e Set Interrupt HLT e Halt WAIT e Wait ESC e Escape (to External Device) LOCK e Bus Lock Prefix 11111000 11110101 11111001 11111100 11111101 11111010 11111011 11110100 10011011 11011xxx 11110000 mod x x x r m Instruction Code 76543210
NOTES AL e 8-bit accumulator AX e 16-bit accumulator CX e Count register DS e Data segment ES e Extra segment Above below refers to unsigned value Greater e more positive Less e less positive (more negative) signed values if d e 1 then ``to'' reg if d e 0 then ``from'' reg if w e 1 then word instruction if w e 0 then byte instruction if mod e 11 then r m is treated as a REG field if mod e 00 then DISP e 0 disp-low and disp-high are absent if mod e 01 then DISP e disp-low sign-extended to 16 bits disp-high is absent if mod e 10 then DISP e disp-high disp-low if r m e 000 then EA e (BX) a (SI) a DISP if r m e 001 then EA e (BX) a (DI) a DISP if r m e 010 then EA e (BP) a (SI) a DISP if r m e 011 then EA e (BP) a (DI) a DISP if r m e 100 then EA e (SI) a DISP if r m e 101 then EA e (DI) a DISP if r m e 110 then EA e (BP) a DISP if r m e 111 then EA e (BX) a DISP DISP follows 2nd byte of instruction (before data if required) except if mod e 00 and r m e then EA e disp-high disp-low if s w e 01 then 16 bits of immediate data form the operand if s w e 11 then an immediate data byte is sign extended to form the 16-bit operand if v e 0 then ``count'' e 1 if v e 1 then ``count'' in (CL) register x e don't care z is used for string primitives for comparison with ZF FLAG SEGMENT OVERRIDE PREFIX
REG is assigned according to the following table
16-Bit (w e 1) 000 AX 001 CX 010 DX 011 BX 100 SP 101 BP 110 SI 111 DI
8-Bit (w e 0) 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH
Segment 00 ES 01 CS 10 SS 11 DS
Instructions which reference the flag register file as a 16-bit object use the symbol FLAGS to represent the file FLAGS e X X X X (OF) (DF) (IF) (TF) (SF) (ZF) X (AF) X (PF) X (CF) Mnemonics Intel 1978
DATA SHEET REVISION REVIEW
The following list represents key differences between this and the -005 data sheet Please review this summary carefully 1 The Intel 8088 implementation technology (HMOS) has been changed to (HMOS-II)
0 0 1 reg 1 1 0
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